1. Field of the Invention
Embodiments of the invention generally relate to a system for annealing semiconductor substrates.
2. Description of the Related Art
Metallization of sub-quarter micron sized features is a foundational technology for present and future generations of integrated circuit manufacturing processes. More particularly, in devices such as ultra large scale integration-type devices, i.e., devices having integrated circuits with more than a million logic gates, the multilevel interconnects that lie at the heart of these devices are generally formed by filling high aspect ratio, i.e., greater than about 4:1,interconnect features with a conductive material, such as copper. Conventionally, deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been used to fill these interconnect features. However, as the interconnect sizes decrease and aspect ratios increase, void-free interconnect feature fill via conventional metallization techniques becomes increasingly difficult. Therefore, plating techniques, i.e., electrochemical plating (ECP) and electroless plating, have emerged as promising processes for void free filling of sub-quarter micron sized high aspect ratio interconnect features in integrated circuit manufacturing processes.
In an ECP process, for example, sub-quarter micron sized high aspect ratio features formed into the surface of a substrate (or a layer deposited thereon) may be efficiently filled with a conductive material. ECP plating processes are generally two stage processes, wherein a seed layer is first formed over the surface features of the substrate (generally through PVD, CVD, or other deposition process in a separate tool), and then the surface features of the substrate are exposed to an electrolyte solution (in the ECP tool), while an electrical bias is applied between the seed layer and a copper anode positioned within the electrolyte solution. The electrolyte solution generally contains ions to be plated onto the surface of the substrate, and therefore, the application of the electrical bias causes these ions to be plated onto the biased seed layer, thus depositing a layer of the ions on the substrate surface that may fill the features.
Once the plating process is completed, the substrate is generally transferred to at least one of a substrate rinsing cell or a bevel edge clean cell. Bevel edge clean cells are generally configured to dispense an etchant onto the perimeter or bevel of the substrate to remove unwanted metal plated thereon. The substrate rinse cells, often called spin rinse dry cells, generally operate to rinse the surface of the substrate (both front and back) with a rinsing solution to remove any contaminants therefrom. Further the rinse cells are often configured to spin the substrate at a high rate of speed in order to spin off any remaining fluid droplets adhering to the substrate surface. Once the remaining fluid droplets are spun off, the substrate is generally clean and dry, and therefore, ready for transfer from the ECP tool.
Thereafter, the cleaned/rinsed substrate is often transferred to an annealing chamber where the substrate is heated to a temperature sufficient to anneal the deposited film. However, the throughput of conventional plating systems may be limited by the availability of the annealing chamber, as an annealing process for a semiconductor substrate after plating may take several minutes. Further, once the annealing process is completed, the annealed substrate generally takes several minutes to cool down to a temperature that allows for transfer of the substrate to another processing chamber or device.
Embodiments of the invention generally provide an annealing system configured for use on a semiconductor processing system, wherein the annealing system is capable of simultaneously processing several substrates in order to increase the annealing throughput. Additionally, embodiments of the invention generally provide an annealing system that is capable of heating a substrate for an annealing process, and then rapidly cooling the substrate in the annealing chamber after the annealing/heating process is complete.